Recently, the data transfer speed between different devices is increasing, and transmission at a high data rate has been realized. In such high data rate transmission, it becomes difficult to secure the skew among parallel signals, in parallel transmission, and hence the limit to the transfer speed has become apparent. Thus, as a matter of preference, serial transmission has come to be utilized for high speed transmission. In such high speed serial transmission, jitter characteristics are felt to be crucial. As the transmission speed increases, the jitter, that is, variations in a signal, which are not of a problem in the low speed transmission, becomes apparent with increase in the transmission speed, and is presented as increasing transmission errors. In case the jitter has increased to more than a certain level, data transmission ceases to be carried out in the normal manner.
In case a transmitter suffers a certain amount of jitter, the jitter ascribable to frequency characteristics of a signal line or to ISI (Inter Symbol Interference) is superposed on the jitter, innate to the transmitter, as a result of signal transmission. In reproducing the digital signal per se, that is, the original digital signal which is to be transmitted, a receiver has to receive a signal added to with the jitter innate to the transmitter and with the jitter produced in the course of transmission. Hence, in a transmission system, jitter tolerance characteristics of the receiver need to be measured at the outset.
One of the methods for measurement of such jitter tolerance characteristics is putting in a jitter component on data. In this case, phase modulation or FM (frequency modulation) is applied to data and the resulting data is sent to a serial I/F device in order to test whether or not CDR (Clock and Data Recovery) of the device is able to receive the data as normally. For this test, it is necessary to construct an environment for measurement in which the data is modulated and the jitter component is put in on the so modulated data.
There is also a method for putting in the jitter component on the clock supplied to the CDR. Receiving normal data by the CDR operating as it takes the clock modulated with the jitter is tantamount to receiving data modulated with the jitter by the CDR operating with the normal clock, and hence a similar test may be conducted for each of these cases. For this test method, it is similarly necessary to construct the environment for measurement.
Meanwhile, in a transmission system, a PLL circuit is used at some times for generating the timing clock for transmission/reception. The PLL circuit is designed for receiving the reference clock to output the clock of a multiple frequency of the reference clock frequency. In such PLL circuit, the routine practice is to generate the clock of the multiple frequency by a voltage controlled oscillator (VCO). There has been known a technique in which a modulated signal generator is mounted directly ahead of the voltage controlled oscillator to impart frequency variations to the output signal from the voltage controlled oscillator, such as to generate the clock containing the jitter component (see Patent Documents 1 and 2, for example).
In a PLL circuit, described in Patent Document 1, the signal output with the frequency corresponding to the voltage of a control signal from the voltage controlled oscillator is divided by a frequency divider. The frequency-divided signal and a reference signal output from the reference signal generator are supplied to a phase frequency detector. An error signal corresponding to the phase difference between the frequency-divided signal and the reference signal is extracted by a low-pass filter from the output signal of the phase frequency detector. An adder adds this error signal to a modulating signal output from a modulating signal generator. The resulting sum signal is supplied as a control signal to the voltage controlled oscillator. The modulating signal generator outputs to the adder a modulating signal of the frequency equal to the jitter frequency as specified and the amplitude corresponding to the amount of the jitter as specified. An output signal from the voltage controlled oscillator is the clock subjected to variations in the frequency and containing the jitter component.
In a PLL circuit, described in Patent Document 2, an adder for adding a signal from a signal generator is included in a phase locked loop composed of a phase comparator, a low-pass filter and a voltage controlled oscillator. With the PLL circuit of the configuration, described above, a large variety of jitter simulations is possible, depending on a pattern of signals, such as a sine wave, a triangular wave and a frequency modulated wave.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2000-230953A (FIG. 2)
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-2-252316 (FIG. 1)